Job Details
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Job Description
- Run logic and physical synthesis.
- Implement the design floor planning, pin placement, and power planning.
- Do the cells placement, routing, and optimization.
- Run clock tree synthesis.
- Analyze critical routes IR drop reports and extract signals parasitic.
- Analyze physical verification reports, including DRC, LVS & antenna checks, and fix the corresponding violations.
- Perform static timing analysis and timing closure.
- Participate in flow development and scripting.
- Solve technical issues in running projects with the team members and guide them to resolve the issues.
- Coach and monitor junior engineers.
- Communicate regularly with customers.
- Conduct review meetings with customers.
- Contribute in process formulation and/or improvement.
Job Requirements
Knowledge:
- B.Sc. degree in Electronics Engineering
- M.Sc. degree in Electronics Engineering is a plus
Years of Experience:
- 3+ years of experience in ASIC backend or digital design
Other Knowledge/ Studies:
- Good knowledge of the device physics
- Very good knowledge of EMIR simulation
Skills
- Oral and written fluency in English
- Excellent knowledge of Microsoft Windows, Word, Power Point, Excel
- Very good knowledge of Linux environment and shell commands
- Very good programming and scripting skills (Shell, Tcl, and/or Perl) is preferred.
Other Skills:
- Excellent knowledge of Synopsys design tools (DC, ICCII, PT, PrimeRail and ICV) and the used flow
Soft Skills:
- Excellent analytical and problem-solving skills along with attention to details is required
- Excellent communication skills
- Self-driven and motivated
- Ability to propose solutions and design enhancements independently, as well as be a key team player