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Job Description
- Develop test plan from specification and architect system level verification environments.
- Develop test-bench components, and coverage metrics.
- Execute RTL/Gate level simulations and analyze results.
- Work with the mixed signal team on the co-simulation and verification of mixed-signal IPs.
- Contribute to design/verification process automation.
Job Requirements
- B.Sc. or M.Sc. in Electronics/Computer Engineering.
- 3-6 Years of experience in developing SV-based verification environments.
- Strong knowledge of Verilog, System Verilog, and object-oriented programming languages.
- Knowledge of at least one standard verification methodology such as VMM, OVM, or UVM.
- Familiarity with RTL design, synthesis, and CDC analysis is a plus.
- Oral and written fluency in English.
- Working knowledge of shell, Perl, and TCL scripting.
- Knowledge of Unix/Linux operating system.
