ASIC Design Engineer

Mixel - Sheraton, Cairo

Applicants for
2 open positions
Experience Needed:
0 to 4 years
Career Level:
Entry Level
Job Type:
Full Time
Education Level:
Bachelor's Degree at least
2 open positions
Travel Frequency:
Minimal travel
About the Job
  • Develop a thorough understanding of system-level design specifications.
  • RTL Coding/Synthesis of the digital part of Mixed Signal IPs.
  • Develop behavioral models for the analog parts of Mixed Signal IPs.
  • Develop advanced verification environment and test-bench components.
  • Working with the mixed signal team on the co-simulation and verification of the IPs.
  • Hardware verification of the digital module using cutting edge FPGA kits.
Job Requirements
  • B.Sc. in Electronics Engineering.
  • 0-4 Years of experience in VLSI Digital Design/Verification.
  • Strong knowledge of Verilog RTL design/simulation.
  • Knowledge of ASIC/FPGA design flows including RTL Synthesis, Place and Route, and Timing Sign-off.
  • Familiarity with System Verilog, RTL/gate verification techniques is a plus.
  • Oral and written fluency in English.
  • Knowledge of Unix/Linux operating system is a plus.
  • Knowledge of shell scripting/programming languages is a plus.
About this Company

Mixel is a leading provider of mixed-signal mobile IPs. We offer a wide portfolio of high-performance mixed-signal connectivity solutions.

Mixel, Inc. is privately held and located in Silicon Valley, USA. Founded in 1998, Mixel’s purpose has always been to... (More)

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