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Job Description
- Digital logic design background is required.
- Knowledge of ASIC Physical Design RTL to GDSII Implementation flow is required
- Knowledge of STA tool and timing closure methodologies is preferred
- Knowledge of Power grid analysis is preferred
- Programming and scripting skills (Shell, Tcl, and/or Perl) is preferred
- Prior experience with Synopsys tools (DC, ICC, PT) and flows is a major plus
Job Requirements
- B.Sc. in Electronics Engineering
- 1-3 years of experience in ASIC backend or Digital design is preferred. Fresh graduates are welcomed to apply.
- Experience in ASIC physical design
- V. good communications skills
- Self-driven and Motivated
- Oral and written fluency in English
- Excellent problem solving and analytical skills