- B.Sc., or M.Sc., in Electronics Engineering.
- Management certification or MBA is a plus.
- Previous experience in leading and managing people.
- Excellent communication and negotiation skills.
- Self-driven, self-Motivated and ambitious.
- Excellent verbal and written communication in English.
- Excellent problem solving and analytical skills.
- Ability to deal with customers from different nationalities.
- International mindset.
- Proven record of delivering physical design projects and automation in physical design.
Previous hands-on experience in;
- ASIC Physical Design RTL to GDSII Implementation flow.
- Physical design implementation (floor-planning, Placement, Routing, CTS, STA) in advanced technologies.
- Understanding complex logic structures and define new IPs targeted at performance and/or area
- STA tool and timing closure methodologies
- Power grid analysis. Understand trade-off between power, performance and area
- Clock tree implication and in-depth understanding of different CTS structures like clock mesh and multi-source CTS
- Physical design verification tasks include creating setup and scripts for DRC, LVS, Antenna and density checks, report generation, analysis, debug and implementing the fixes in the physical design database.
- DFM checks for the advanced node designs
- Synthesis and Design for Testability (DFT) flow
- Low power design closure UPF based implementation
- Timing .lib generation
- Using Synopsys tools and flows
About this Company
Si-Vision has been in business since 2007, with more than 350 years of collective experience and serving Tier-1 customers all over the globe. The Silicon Vision team has broad experience in RF Circuits and Systems, Digital and Backend Designs.
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In July 16, 2015...