fatma khaled

GRADUATION PROJECT: •Accelerating aware Machine Learning algorithms design and verification (SqueezeNet).ImplementIing the whole CNN architecture (SqueezeNet) on FPGA virtex UltraScale with minimum resources and latency time by using some optimization techniques. Its function is to classify an input image into 10 classes chosen from ImageNet . During the Project, I have gained an experience in RTL designing, HDL and MATLAB modeling of different layers of any CNN architecture blocks, fine-tuning using keras and finally testing the blocks of the CNN architecture.the design was safely implemented on virtex 7. -Implementing Complete Microprocessor using FPGA and VHDL -Wireless, Mobile controlled Ground Drawing Robot -RF Power divider Design & EM Simulation using ADS -IC design of an integer binary divider using static CMOS approach, including the circuit floorplan with the I/O pads using the 0.5 µm N well CMOS process and the CUSCLIB library cells by L-Edit tool. (VLSI course project).