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Jr. Digital Verification Engineer

Si-Vision
Sheraton, Cairo
Posted 4 years ago
98Applicants for1 open position
  • 86Viewed
  • 11In Consideration
  • 83Not Selected
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Job Details

Experience Needed:
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Skills And Tools:

Job Description

  • Extract verification requirements from system specification.
  • Contribute in generating the verification plan for block level.
  • Contribute in architecting the verification environment which is mapped from the verification plan for block level.
  • Implement the verification environment using UVM.
  • Debug test failures and work with designers to develop fixes.
  • Work on achieving targeted coverage goal for the verification sign off for block level.
  • Perform Co-simulation activities and work with analog and digital teams to gather Co-sim requirements and develop fixes on the interaction between analog and digital parts in the IP.

Job Requirements

Education

  • B.Sc. in Electronics Engineering

Years of Experience

  • 0 - 1 year of experience

Other Knowledge/ Studies

  • Oral and written fluency in English
  • Microsoft office
  • Excellent knowledge of ASIC Design Flow.
  • Excellent knowledge of Verilog.
  • Knowledge about test bench architecting, designing and implementation.
  • Have a debugging skill in both functional and gate-level simulations.
  • Programming skills in any object-oriented language.
  • Knowledge of object-oriented object concepts and design patterns.
  • Knowledge of coverage driven verification concepts.
  • Knowledge of any of an advanced verification methodology (OVM/UVM/VMM).
  • Knowledge of any scripting language ( PERL, TCL, Shell script, …)
  • Experience with Assertion Based Verification and/or Formal Verification would be an asset.

Abilities

  • Self-driven and Motivated
  • High communication skills
  • Detailed Oriented
  • Ownership and dedication

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