Job Details
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Job Description
Main Responsibilities:
- Study assigned blocks, analyze circuits carefully and work on the hand analysis.
- Understand the required performance, targeted specifications, and the trade-off between different performance metrics.
- Prepare concept reviews covering circuits and test benches in detail.
- Write behavioral models of different circuit blocks for system-level simulations.
- Simulate and verify designed circuits using EDA tools.
- Debug performance degradation to find out the root cause.
- Being capable of solving faced issues in different design phases.
- Understand the interface with other blocks (if any) and work with other team members to optimize it.
- Develop verification plans for different analog building blocks.
- Develop and execute characterization plans of the designed blocks, systems, and chips.
- Check different reliability verifications such as EM, IR, and Aging.
- Do timing models using custom static timing analysis tools.
- Deliver corresponding documentation as per the design process.
- Working with layout team on physical design optimization.
- Evaluate post layout performance using extraction EDA tools.
- Build top-level schematics and test benches, in addition, to coordinating and handling top-level simulations.
- Conduct design review meetings.
- Conduct customer meetings and communicate with customers on assigned requests.
- Coach and monitor junior engineers.
- Contribute to process formulation and improvement.
- Share technical expertise and contribute by technical opinion (if possible) in design reviews conducted by others team members.
Job Requirements
Requirements:
- B.Sc. degree in Electronics Engineering.
- M.Sc. degree in Electronics Engineering is a plus.
- 3+ years of experience in analog and mixed-signal IC development
- Deep understanding of analog design concepts and trade-offs between area, power, noise, and/or mismatch
- Deep knowledge of one of the following CMOS circuits: op-amps, voltage regulators, bias circuits, oscillators, analog-digital conversion, phase-locked loops, high-speed interfaces, or any relevant circuits.
- Excellent knowledge of design/simulation tools such as Synopsys, Cadence, and/or Mentor tools or any relevant tools.
- Good knowledge of analog layout techniques.
- Good knowledge of timing concepts.
- Very Good knowledge of custom timing static analysis tools (Synopsys NanoTime, Synopsys SiliconSmart) is a plus
- Good knowledge of EM and aging simulations is a plus.
- Good knowledge in behavioral modeling (Verilog, Verilog AMS) is a plus
