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Job Description
- Candidate is responsible for participating in the verification of the digital part in the mixed signal IPs and digital controller IPs.
- He will gather verification requirements, contribute in the verification planning, implement the verification environment, running simulations and achieve coverage targets.
- Candidate also shall perform post APR simulations and Co-simulation activities for our Mixed signal IPs.
Job Requirements
- Excellent knowledge of using verification planner tool to monitor verification progress.
- Excellent MS Project skills (or any similar planning tool).
- Project Management skills
- Excellent Knowledge of coverage-driven verification concepts.
- Excellent Knowledge of any of the advanced verification methodologies (OVM/UVM/VMM).
- Excellent knowledge in verification environment architecting, designing and implementation.
- Excellent experience in developing and maintaining both block level and top-level verification environments for digital systems.
- Excellent debugging skills in both functional and gate level simulations.
- Experience with Assertion Based Verification languages (SVA, PSL...).
- Knowledge of any scripting language (PERL, TCL, Shell script , …)
- Experience with power-aware verification and knowledge of writing of writing UPF would be an asset.
- Experience with Formal Verification would be an asset.
