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Job Description
- Communicate efficiently and closely with the customer.
- Work in an agile-based environment and adapt to changes.
- Accomplish tasks using innovative techniques.
- Keep track on tasks’ timeline and report the progress effectively on a regular basis.
- Document and Present thoughts and ideas in a clear and illustrative way.
- Responsible for cell-level IC layout using Custom IC layout tools.
- Extract and summarize vital and useful information from technical documents.
- Work closely with the design team throughout the design cycle to gather all the design requirements and layout constraints.
- Estimate (block-level/ Top-level) area and do efficient floor-plans while considering the appropriate layout effects.
- Implement block-level routing with the full-awareness of interconnects parasitics, reliability, and manufacturability.
- Perform physical verification (LVS/DRC/Antenna/EMIR/PERC/PEX) on the block-level.
- Debug and analyze the parasitic extraction and post layout verification results.
- Sign-off the final layout design (Block-level/Top level) while meeting all the requirements and quality metrics.
- Develop scripts using programming languages such as Tcl, Perl, and shell is a plus.
- Apply the layout process effectively to ensure applying of layout design best practice, and participate in the continual improvement of the team process
- Aware of full chip level layout design and verification.
- Mentoring other team members and reviewing their technical output.
Job Requirements
- B.Sc. in Electronics Engineering
- 3+ Years of Experience
- Able to work and communicate effectively with in the team.
- Able to multi-task effectively in a fast-paced work environment.
- Able to monitor Junior/Standard layout engineers in their daily task development
- Full awareness of IC layout design flows and its fabrication steps.
- Aware of Analog circuit design basics.
- Full awareness of Layout design methodologies such as device matching techniques, signal conditioning and protection techniques.
- Full awareness of advanced Layout design topics such as ESD Protection circuits, Bonding and packaging layout-related techniques, and full awareness of the layout effects related to advanced technologies.
Skills
- Oral and written fluency in English
- Microsoft office
- Linux and Windows operating systems.
- Layout Design tools: Synopsys/Custom_Compiler, Cadence/Virtuoso.
- Layout Verification tools: Synopsys/IC-Validator, Mentor/Calibre, Cadence/PVS.
Other Skills
- Scripting Languages: Tcl, Perl, Shell.
- Presentation skills is a plus.
- Time management.
Abilities
- Excellent problem solving and analytical skills.
- Ability to work independently as well as a key team player.
- Being agile and adapting to changes.
- Ability to work and communicate effectively within the team.
- Multi-tasking in a fast-paced work environment.