Job Details
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Job Description
- Responsible for synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out.
- Work on methodology with help of local and external CAD/EDA teams for faster design convergence .
Job Requirements
Experienced Design Implementation Engineers
- More than 10 years (DI10)
- More than 5 years (DI5)
Experience in:
- Synopsys/Cadence synthesis, DFT (at speed scan, memory BIST), static timing analysis, equivalence checking, power simulations.
- Synopsys/Cadence P&R, floorplanning, CTS, physical design and verification, LVS/DRC, extraction, Electro migration, IR drop.
Skills:
- A strong digital design verification background, including full-chip verification.
- Must have practical experience with details of verification environments and tool flows.
- Must have experience in UVM test environment development, test-bench components, scoreboards, agents, drivers, monitors.
- Ability to collaborate and resolve issues w.r.t. constraints validation, verification, STA, Physical design, etc.
- Should have good knowledge & experience in low power design implementation, high performance design closure & multi scenario timing convergence
- Experience in Physical Design Execution is required Independent planning and execution of Netlist-to-GDSII.
Additional requirements:
- Excellent command of the English language.
- Ability to work in a team environment.
- Ability to lead small teams of designers.
- Good self-motivation and time management skills.
- Full-time commitment.
Minimum Education Requirement:
- A bachelors degree with high grades in computer or electrical engineering.
Preferred:
- Experience with communication system design/verification is an advantage.
- Honors students.
- A relevant MSc. degree would be an advantage.
- Experience in 65nm or lower geometries .
