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Job Description
ASIC Verification Engineer @Symmid is now needed with the below Requirements:
- Strong background in ASIC design flow [RTL to GDS].
- Strong coding skill in Verilog/VHDL for synthesisable RTL and behavioral modeling.
- System Verilog, Verilog-AMS is a plus.
- Working experience in FPGA design, debugging.
- Strong verification skills using SVA, UVM, OVM, DFT.
- Scripting language experience a plus (perl, Makefile, bash, tcl, ... etc.).
- Familiar with C coding, MATLAB is a plus.
- Familiar with ECO flow, FMEA is a plus.
- Able to work independently and in a team environment. Able to lead projects/team.
Job Requirements
Requirements:
- Bachelors degree in engineering with 3+ years of relevant experience in RTL functional verification.
- Processor blocks verification at MLV and Top level is big plus.
- Microprocessor architecture knowledge
- HDL and Verification languages: SystemVerilog, Verilog.
- Testbench Methodology : UVM, VMM.
- Programming skills: C, assembly, Perl, makefile generation.
- Tools: RTL Simulators, eg VCS.
- Experience with multi-site development is helpful.
Written and Verbal skills:
- Creation, modification and review of test documentation:
- Testplans, procedures, test scenarios, test reports
- Ability to present verification results to management
- Ability to describe problems in the defect tracking system
Analytical skills:
- Analysis of verification requirements to close out on product release
- Ability to analyze test results and provide reports
- Self-motivated team player able to thrive in a fast-paced engineering environment