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Job Description
- Work with design team to define co-simulation test plan.
- Work with the verification team to modify existing UVM verification environment to co-simulate mixed signal designs having both digital and analog circuits coexisting with each other.
- Debug simulation failures in both analog and digital domains.
- Run and debug functional tests and performance tests which verify timing and power specifications.
- Interact with analog design and digital design teams during co-simulation debugging.
Job Requirements
Education
- B.Sc. in Electronics Engineering
Years of Experience
- 0 - 1
Other Knowledge/ Studies
- Oral and written fluency in English
- Microsoft office
- Excellent knowledge of ASIC Design Flow.
- Excellent knowledge of Verilog.
- Knowledge about analog circuitry.
- Experience with digital simulators such as VCS.
- Experience with SPICE simulators such as XA and FineSim.
- Knowledge about test bench architecting, designing and implementation.
- Have a debugging skill in both functional and gate-level simulations.
- Programming skills in any object-oriented language.
- Knowledge of object-oriented object concepts and design patterns.
- Knowledge of coverage driven verification concepts.
- Knowledge of any of an advanced verification methodology (OVM/UVM/VMM).
- Knowledge of any scripting language ( PERL,TCL, Shell script , …)
- Experience with Assertion Based Verification and/or Formal Verification would be an asset.
