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Senior Digital Verification Engineer

Si-Vision
Sheraton, Cairo
Posted 5 years ago
7Applicants for1 open position
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Job Details

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Job Description

  • Responsible for participating in the whole process of functional verification for Digital part of Analog Mixed SoCs, The verification process begins from acquiring system
  • Design requirements and write verification requirements and completing the test plan
  • Implementing coverage driven environment contains constraint random stimulus for both block level and system level.
  • Has to work closely with system group, architects, design and verification teams.

Job Requirements

Minimum Requirement:

  • BS / MS in Electronics or Computer Engineering with +4 years of experience.
  • Excellent Knowledge of coverage driven verification concepts.
  • Excellent Knowledge of any of an advanced verification methodology (OVM/UVM/VMM).
  • Experience with Assertion-Based Verification languages (SVA, PSL...).
  • Knowledge of any scripting language (PERL, TCL, Shell script,…)
  • Excellent knowledge in test bench architecture, design and implementation.
  • Excellent debug skills in both functional and gate level simulations.
  • Develop and maintain both block level and top-level verification environments for Mixed Signal IPs.
  • High communication skills with team members

Preferred Requirement:

  • Experience with Interface IPs (USB, PCIe, SATA ... etc.) is a major plus
  • Experience with power aware verification and knowledge of writing of writing UPF would be an asset.
  • Experience with Formal Verification would be an asset.
  • Experience with verification using an emulator would be an asset.

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