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Job Description
- Low-power implementation methods: CLP, power and IR drop reduction methods
- Develop project plans and follow-up on implementation to ensure quality of design and on-time delivery of outputs.
- Responsible for handling technical issues and for guiding the team to resolve these issues.
- Physical design verification tasks include creating setup and scripts for DRC, LVS, Antenna and density checks, report generation, analysis, debug and implementing the fixes in the physical design database.
- Synthesis and Design for Testability (DFT) flow knowledge
- Prior experience with Synopsys tools and flows is a major plus
- Programming and scripting skills (Shell, Tcl, and/or Perl).
- Responsible for the technical issues in projects running with the team members and guide them to resolve the issues.
Job Requirements
- B.Sc. or M.Sc. in Electronics Engineering with 4-7 years of experience.
- Excellent communications skills
- Self-driven and Motivated
- Oral and written fluency in English.
- Knowledge of Low power design closure UPF based implementation is a plus
- Digital logic design background is required.
- Knowledge of ASIC Physical Design RTL to GDSII Implementation flow
- STA tool and timing closure methodologies
- Understand trade off between power, performance and area