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Job Description
- Digital logic design background is required.
- Experience in ASIC Physical Design RTL to GDSII Implementation flow
- Physical design implementation (floor-planning, Placement, Routing, CTS, STA) in advanced technologies.
- Experience working on complex PHYs and related Sub Systems
- Ability to understand complex logic structures and define new IPs targeted at performance and/or area
- STA tool and timing closure methodologies
- Power grid analysis. Understand tradeoff between power, performance and area
- Clock tree implication and in-depth understanding of different CTS structures like clock mesh and multi-source CTS
- Low-power implementation methods: CLP, power and IR drop reduction methods
- Physical design verification tasks include creating setup and scripts for DRC, LVS, Antenna and density checks, report generation, analysis, debug and implementing the fixes in the physical design database.
- DFM checks for the advanced node designs.
- Programming and scripting skills (Shell, Tcl, and/or Perl).
- Synthesis and Design for Testability (DFT) flow knowledge
- Experience with Low power design closure UPF based implementation
- Knowledge of Timing .lib generation
- Prior experience with Synopsys tools and flows is a major plus
- Proficiency in semiconductor device physics and transistor characteristics.
- Responsible for the technical issues in projects running with the team members and guide them to resolve the issues.
Job Requirements
- B.Sc. or M.Sc. in Electronics Engineering with 3-5 years of experience in ASIC physical design
- Excellent communications skills
- Self-driven and Motivated
- Oral and written fluency in English
