Digital Design Engineer

• Develop and execute detailed block-level and chip-level digital designs.
• Write and verify RTL code (Verilog/VHDL) for digital sub-systems of system-on-a-chip (SOC).
• Synthesis of RTL code.
• Run static timing verification on the gate-level netlist with parasitics
• Writing test plans and test-bench development.
• Generation of required documentation and contribution to the validation and debugging of the fabricated silicon.

Required Skills

• Design and verification experience at the RTL and gate-level (Verilog/VHDL)
• Familiar with IC design and verification tools on (VCS, NC-SIM, ModelSim, etc).
• Familiar with synthesis flow and tools
• Knowledge of high speed and low power digital design techniques
• Good documentation, communication, and presentation skills.
• Excellent problem solving and analytical skills.
• Knowledge of P&R and DFT tools is a plus.
• Prior Experience with Synopsys tools and flows is a major plus