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Job Description
- Develop and execute detailed block-level and chip-level digital designs.
- Write and verify RTL code (Verilog/VHDL) for digital sub-systems of system-on-a-chip (SOC).
- Synthesis of RTL code.
- Run static timing verification on the gate-level netlist with parasitics
- Writing test plans and test-bench development.
- Generation of required documentation and contribution to the validation and debugging of the fabricated silicon.
Job Requirements
- 0-3 BS or MS in Electrical Engineering with background in CMOS ASIC/FPGA design
- Excellent communications skills.
- Ability to work independently as well as a key team player.
- Oral and written fluency in English.
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