Senior Layout Engineer @ Vidatronic

iHub - Heliopolis, Cairo

Applicants for
1 open position
Experience Needed:
More than 3 years
Career Level:
Experienced (Non-Manager)
Job Type:
Full Time
Arabic, English
1 open position
About the Job
    • Implementing analog and mixed-signal layout.
    • Leading full chip floor-planning and integration.
    • Managing tape-out activities with full accountability for on-time delivery to foundries.
    • Working closely with design engineers and other layout designers to guarantee high circuit performance.
    • Mentoring other layout designers in the proper use of guard rings and isolation techniques.
    • Performing and/or supervising layout generation and changes as required.
    • Assisting design team with post-layout RC extractions for simulations and optimization.
    • Maintaining well-organized records of the work and milestone commitments within tight schedules.
    • Documenting and summarizing layout design and hosting well-organized design reviews.
                    Job Requirements
                    • Bachelor’s degree in Electronics and Electrical Communications Engineering and 3+ years experience.
                    • Experience with Layout tools based on Cadence Virtuoso, Tanner, and Calibre.
                    • Experience with full-chip responsibilities and integration and proof of consistent on-time delivery.
                    • Possesses excellent floor-planning and layout integration skills.
                    • Demonstrated ability to perform complex analog or digital layout tasks within short schedules and constrained environments that require resourceful solutions.
                    • Excellent LVS/DRC trouble-shooting and debugging skills.
                    • Experience with layout of analog circuits with attention to matching, common-centroid layout, isolation and shielding is required.
                    • Experience with isolation wells for voltage regulators or high-current designs.
                    • Expertise in ESD/latch up/packaging support and other best practices for high performance analog layouts.
                    • Familiar with layout of analog circuits in deep sub-micron CMOS processes (Planar, FinFeT, and SOIs) and of second order layout effects in those processes that affect circuit performance.
                    • Experience with RFIC layout techniques is a plus.
                    • Experience with layout of custom digital circuits.
                    • Exposure to Place-and-Route tools and their integration considerations is a plus.
                    • Scripting skills for enhanced LVS/DRC verification is another plus.
                    About this Company

                    The iHub is a non-for-profit entity that aims at increasing the hands-on experience and boosting innovation within students. The iHub exists at Ain Shams, Cairo, Alexandria and Minia Universities The iHub partners with many industry companies and startups in providing... (More)

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