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Job Description
Main Responsibilities:
- Run logic and physical synthesis.
- Implement the design floor planning, pin placement, and power planning.
- Do the cells placement, routing, and optimization.
- Run clock tree synthesis.
- Analyze critical routes IR drop reports and extract signals parasitic.
- Analyze physical verification reports, including DRC, LVS & antenna checks, and fix the corresponding violations.
- Perform static timing analysis and timing closure.
- Participate in flow development and scripting.
- Solve technical issues in running projects with the team members and guide them to resolve the issues.
- Coach and monitor junior engineers.
- Communicate regularly with customers.
- Conduct review meetings with customers.
- Contribute to process formulation and/or improvement.
Job Requirements
- B.Sc. degree in Electronics Engineering.
- M.Sc. degree in Electronics Engineering is a plus.
- 3+ years of experience in ASIC backend OR similar field (digital design, layout, FPGA design, etc ..).
- Acceptable digital logic design basic concepts
- Excellent knowledge of digital timing violations is a plus
- Acceptable knowledge of ASIC Physical Design RTL to GDSII
- Very good knowledge of Linux environment and shell commands
- Very good programming and scripting skills (Shell, Tcl, and/or Perl) are preferred.
- Acceptable knowledge of Synopsys design tools (DC, ICCII, PT, PrimeRail, and ICV) and the user flow.
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