Job Details
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Job Description
Verification Engineer responsible for participating in the whole process of functional verification for Digital part of Analog Mixed SoCs , The verification process begins from acquiring system design requirements and write verification requirements and completing the test plan then implementing coverage driven environment contains constraint random stimulus for both block level and system level. Verification Engineer also responsible for Co-Simulating analog and digital circuits together using AMS Simulators. He/She has to work closely with system group, architects, design and verification teams.
Job Requirements
Required Skills:
- Excellent knowledge of ASIC Design Flow.
- Extensive experience with Verilog.
- Excellent knowledge in test bench architecture, design and implementation.
- Excellent debug skills in both functional and gate level simulations.
- Programming skills in any object oriented language.
- Knowledge of object oriented object concepts and design patterns.
Qualifications:
- 0 – 5 years of experience.
- Knowledge of coverage driven verification concepts.
- Knowledge of any of an advanced verification methodology (OVM/UVM/VMM).
- Knowledge of any scripting language ( PERL ,TCL , Shell script , …)
- Experience with Assertion Based Verification and/or Formal Verification would be an asset.
- Knowledge of Co-simulation for digital and analog parts of the system using AMS simulators.
- BS / MS in Electronics or Computer Engineering
- High communication skills with team members
